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INTEGRATED CIRCUITS
DATA SHEET
PCF8576 Universal LCD driver for low multiplex rates
Product specification Supersedes data of 1997 Nov 18 File under Integrated Circuits, IC12 1998 Feb 06
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Static drive mode 1 : 2 multiplex drive mode 1 : 3 multiplex drive mode 1 : 4 multiplex drive mode Oscillator Internal clock External clock Timing Display latch Shift register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 11.1 11.2 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 18
PCF8576
CHARACTERISTICS OF THE I2C-BUS Bit transfer START and STOP conditions System configuration Acknowledge PCF8576 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS Typical supply current characteristics Typical characteristics of LCD outputs APPLICATION INFORMATION Chip-on-glass cascadability in single plane BONDING PAD LOCATIONS PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
1 FEATURES
PCF8576
* Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers * May be cascaded for large LCD applications (up to 2560 segments possible) * Cascadable with 24-segment LCD driver PCF8566 * Optimized pinning for plane wiring in both single and multiple PCF8576 applications * Space-saving 56-lead plastic very small outline package (VSO56) * Very low external component count (at most one resistor, even in multiple device applications) * Compatible with chip-on-glass technology * Manufactured in silicon gate CMOS process. 2 GENERAL DESCRIPTION
* Single-chip LCD controller/driver * Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing * Selectable display bias configuration: static, 12 or 13 * Internal LCD bias generation with voltage-follower buffers * 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements * 40 x 4-bit RAM for display data storage * Auto-incremented display data loading across device subaddress boundaries * Display memory bank switching in static and duplex drive modes * Versatile blinking modes * LCD and logic supplies may be separated * Wide power supply range: from 2 V for low-threshold LCDs and up to 9 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs * Low power consumption * Power-saving mode for extremely low power consumption in battery-operated and telephone applications * I2C-bus interface * TTL/CMOS compatible 3 ORDERING INFORMATION
The PCF8576 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCF8576 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).
PACKAGE TYPE NUMBER NAME PCF8576T PCF8576U PCF8576U/2 PCF8576U/5 PCF8576U/7 PCF8576U/10 PCF8576U/12 VSO56 - - - - FFC FFC chip in tray chip with bumps in tray unsawn wafer chip with bumps on tape chip on film frame carrier (FFC) chip with bumps on film frame carrier (FFC) DESCRIPTION plastic very small outline package; 56 leads VERSION SOT190-1 - - - - - -
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BP0 BP2 BP1 BP3 13 VDD 5 R 14 15 16 S0 to S39 40 17 to 56 DISPLAY SEGMENT OUTPUTS BACKPLANE OUTPUTS R LCD VOLTAGE SELECTOR DISPLAY LATCH R VLCD 12 4 CLK SYNC 3 TIMING BLINKER DISPLAY CONTROLLER OSC 6 OSCILLATOR POWERON RESET COMMAND DECODER INPUT FILTERS I 2C - BUS CONTROLLER 10 SA0
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Philips Semiconductors
Universal LCD driver for low multiplex rates
BLOCK DIAGRAM
LCD BIAS GENERATOR
SHIFT REGISTER
PCF8576
INPUT BANK SELECTOR DISPLAY RAM 40 x 4 BITS OUTPUT BANK SELECTOR
4
DATA POINTER
V SS SCL SDA
11 2 1
SUBADDRESS COUNTER 7 A0 8 A1 9 A2
MBK276
Product specification
PCF8576
Fig.1 Block diagram (for VSO56 package; SOT190-1).
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
5 PINNING SYMBOL SDA SCL SYNC CLK VDD OSC A0 to A2 SA0 VSS VLCD BP0, BP2, BP1 and BP3 S0 to S39 PIN 1 2 3 4 5 6 7 to 9 10 11 12 13 to 16 17 to 56 I2C-bus I2C-bus serial clock input cascade synchronization input/output external clock input/output supply voltage oscillator input I2C-bus subaddress inputs I2C-bus slave address input; bit 0 logic ground LCD supply voltage LCD backplane outputs LCD segment outputs DESCRIPTION serial data input/output
PCF8576
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
handbook, halfpage
SDA SCL SYNC CLK VDD OSC A0 A1 A2
1 2 3 4 5 6 7 8 9
56 S39 55 S38 54 S37 53 S36 52 S35 51 S34 50 S33 49 S32 48 S31 47 S30 46 S29 45 S28 44 S27 43 S26
SA0 10 VSS 11 VLCD 12 BP0 13 BP2 14
PCF8576T
BP1 15 BP3 16 S0 17 S1 18 S2 19 S3 20 S4 21 S5 22 S6 23 S7 24 S8 25 S9 26 S10 27 S11 28
MBK278
42 S25 41 S24 40 S23 39 S22 38 S21 37 S20 36 S19 35 S18 34 S17 33 S16 32 S15 31 S14 30 S13 29 S12
Fig.2 Pin configuration; SOT190-1.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6 FUNCTIONAL DESCRIPTION
PCF8576
The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576. The internal oscillator is selected by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
The PCF8576 is a versatile peripheral device designed to interface to any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.3. Table 1 Selection of display configurations NUMBER OF BACKPLANES 4 3 2 1 SEGMENTS 160 120 80 40
7-SEGMENTS NUMERIC DIGITS 20 15 10 5 INDICATOR SYMBOLS 20 15 10 5
14-SEGMENTS ALPHANUMERIC DOT MATRIX CHARACTERS 10 8 5 2 INDICATOR SYMBOLS 20 8 10 12 160 dots (4 x 40) 120 dots (3 x 40) 80 dots (2 x 40) 40 dots (1 x 40)
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V
DD R
tr 2CB 5 SDA SCL OSC
V DD 1 2 6 7 ROSC A0 8 A1 9
V 12
LCD LCD PANEL (up to 160 elements)
HOST MICROPROCESSOR/ MICROCONTROLLER
17 to 56 40 segment drives
PCF8576
13 to 16 10 11 A2 SA0 V SS
4 backplanes
MBK277
V SS
Fig.3 Typical system configuration.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.1 Power-on reset 6.3 LCD voltage selector
PCF8576
At power-on the PCF8576 resets to a starting condition as follows: 1. All backplane outputs are set to VDD. 2. All segment outputs are set to VDD. 3. The drive mode `1 : 4 multiplex with 13bias' is selected. 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 5). 6. The I2C-bus interface is initialized. 7. The data pointer and the subaddress counter are cleared. should be avoided for 1 ms Data transfers on the following power-on to allow completion of the reset action. 6.2 LCD bias generator I2C-bus
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of Vop = VDD - VLCD and the resulting discrimination ratios (D), are given in Table 2. A practical value for Vop is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is Vop > 3Vth approximately. Multiplex drive ratios of 1 : 3 and 1 : 4 with 12bias are possible but the discrimination and hence the contrast ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or 21 ---------- = 1.528 for 1 : 4 multiplex). 3 The advantage of these modes is a reduction of the LCD full-scale voltage Vop as follows: * 1 : 3 multiplex (12bias): Vop = 6 x V off rms = 2.449 Voff(rms)
The full-scale LCD voltage (Vop) is obtained from VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin 12. Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VDD and VLCD. The centre resistor can be switched out of the circuit to provide a 12bias voltage level for the 1 : 2 multiplex configuration.
* 1 : 4 multiplex (12bias): ( 4 x 3) Vop = ----------------------- = 2.309 Voff(rms) 3 These compare with Vop = 3 Voff(rms) when 13bias is used.
Table 2
Preferred LCD drive modes: summary of characteristics NUMBER OF LCD BIAS CONFIGURATION static
1 2 1 3 1 3 1 3
LCD DRIVE MODE BACKPLANES static 1:2 1:2 1:3 1:4 1 2 2 3 4 LEVELS 2 3 4 4 4
V off(rms) -------------------V op 0 0.354 0.333 0.333 0.333
V on(rms) -------------------V op 1 0.791 0.745 0.638 0.577
V on(rms) D = -------------------V off(rms) 2.236 2.236 1.915 1.732
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.4 6.4.1 LCD drive mode waveforms STATIC DRIVE MODE 6.4.3 1 : 3 MULTIPLEX DRIVE MODE
PCF8576
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.4. 6.4.2 1 : 2 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.7. 6.4.4 1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.8.
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8576 allows use of 1 bias or 1 bias in this mode as shown in Figs 5 and 6. 2 3
T frame V DD BP0 V LCD V DD Sn V LCD VDD Sn 1 V LCD V op (a) waveforms at driver state 1 (on) state 2 (off) LCD segments
state 1
0
Vop V op
state 2
0
Vop
(b) resultant waveforms at LCD segment
MBE539
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = V op V state2(t) = V S V off(rms) = 0 V
n+1
(t) - V BP0(t)
Fig.4 Static drive mode waveforms (Vop = VDD - VLCD).
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
T frame VDD BP0 (VDD V LCD VDD BP1 (VDD V LCD VDD Sn V LCD VDD Sn 1 V LCD (a) waveforms at driver Vop V op /2 state 1 0 V op /2 Vop Vop V op /2 state 2 0 V op /2 Vop (b) resultant waveforms at LCD segment
MBE540
LCD segments V LCD )/2 state 1 state 2 V LCD )/2
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.791V op V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.354V op
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 12bias (Vop = VDD - VLCD).
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
T frame VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD (a) waveforms at driver Vop 2Vop /3 Vop /3 0 Vop /3 2Vop /3 Vop Vop 2Vop /3 Vop /3 0 Vop /3 2Vop /3 Vop LCD segments
BP0
state 1 state 2
BP1
Sn
Sn 1
state 1
state 2
(b) resultant waveforms at LCD segment
MBE541
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.745V op V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.333V op
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 13bias (Vop = VDD - VLCD).
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
T frame VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD (a) waveforms at driver Vop 2V op /3 Vop /3 0 Vop /3 2V op /3 Vop Vop 2V op /3 Vop /3 0 Vop /3 2V op /3 Vop LCD segments
BP0
state 1 state 2
BP1
BP2/S23
Sn
Sn 1
Sn 2
state 1
state 2
(b) resultant waveforms at LCD segment
MBE542
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.638V op V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.333V op
Fig.7 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD - VLCD).
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
T frame VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD VDD V DD Vop /3 VDD 2Vop /3 VLCD (a) waveforms at driver Vop 2Vop /3 V op /3 0 V op /3 2Vop /3 Vop Vop 2Vop /3 V op /3 0 V op /3 2Vop /3 Vop LCD segments
BP0
state 1 state 2
BP1
BP2
BP3
Sn
Sn 1
Sn 2
Sn 3
state 1
state 2
V state1(t) = V S (t) - V BP0(t)
n
V on(rms) = 0.577V op (b) resultant waveforms at LCD segment
MBE543
V state2(t) = V S (t) - V BP1(t)
n
V off(rms) = 0.333V op
Fig.8 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD - VLCD).
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.5 6.5.1 Oscillator INTERNAL CLOCK 6.6 Timing
PCF8576
The internal logic and the LCD drive signals of the PCF8576 are timed either by the internal oscillator or from an external clock. When the internal oscillator is used, pin OSC should be connected to pin VSS. In this event, the output from pin CLK provides the clock signal for cascaded PCF8566s in the system. Where resistor Rosc to VSS is present, the internal oscillator is selected. The relationship between the oscillator frequency on pin CLK (fclk) and Rosc is shown in Fig.9.
The timing of the PCF8576 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal SYNC maintains the correct timing relationship between the PCF8576s in the system. The timing also generates the LCD frame frequency which it derives as an integer multiple of the clock frequency (see Table 3). The frame frequency is set by the MODE SET commands when internal clock is used, or by the frequency applied to pin CLK when external clock is used. The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. When a device is unable to digest a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. Table 3 LCD frame frequencies FRAME FREQUENCY f clk -----------2880 f clk --------480 NOMINAL FRAME FREQUENCY (Hz) 64
10 3
f clk (kHz)
MBE531
102
max
min
10 10 2
103
R osc (k)
10 4
PCF8576 MODE
3.4 x 10 7 f clk ----------------------- ( kHz ) R osc
Normal mode
Fig.9 Oscillator frequency as a function of Rosc.
Power-saving mode
64
6.5.2
EXTERNAL CLOCK
6.7
Display latch
The condition for external clock is made by connecting pin OSC to pin VDD; pin CLK then becomes the external clock input. The clock frequency (fclk) determines the LCD frame frequency and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data rate of 100 kHz, fclk should be chosen to be above 125 kHz. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 1998 Feb 06 14
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM. 6.8 Shift register
The shift register serves to transfer display information from the display RAM to the display latch while previous data is displayed.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.9 Segment outputs
PCF8576
correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 40 segments operated with respect to backplane BP0 (see Fig.10). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data is transmitted to the PCF8576 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.11; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.11, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses.
The LCD drive section includes 40 segment outputs pins S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. When less than 40 segment outputs are required the unused segment outputs should be left open-circuit. 6.10 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be connected together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.11 Display RAM
The display RAM is a static 40 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on state of the corresponding LCD segment; similarly, a logic 0 indicates the off state. There is a one-to-one
display RAM addresses (rows) / segment outputs (S) 0 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3
MBE525
1
2
3
4
35
36
37
38
39
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.12 Data pointer
PCF8576
The PCF8576 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of bit 0 contents. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.15 Input bank selector
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.11. The data pointer is automatically incremented in accordance with the chosen LCD configuration. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode) or by two (1 : 4 multiplex drive mode). 6.13 Subaddress counter
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using the BANK SELECT command. The input bank selector functions independent of the output bank selector. 6.16 Blinker
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1 : 3 multiplex mode). 6.14 Output bank selector
The display blinking capabilities of the PCF8576 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in Table 4. An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command.
This selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 4 Blinking frequencies NORMAL OPERATING MODE RATIO - f clk --------------92160 f clk ------------------184320 f clk ------------------368640 POWER-SAVING MODE RATIO - f clk --------------15360 f clk --------------30720 f clk --------------61440
PCF8576
BLINKING MODE Off 2 Hz
NOMINAL BLINKING FREQUENCY blinking off 2 Hz
1 Hz
1 Hz
0.5 Hz
0.5 Hz
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drive mode LCD segments
a f g e d Sn 6 c b Sn Sn Sn 7 DP 1 BP0
Philips Semiconductors
Universal LCD driver for low multiplex rates
LCD backplanes
display RAM filling order
transmitted display byte
Sn Sn Sn
2 3 4 5
n bit/ BP 0 1 2 3 c x x x
n1 b x x x
n2 a x x x
n3 f x x x
n4 g x x x
n5 e x x x
n6 d x x x
n7 MSB DP x x x cbaf LSB g e d DP
static
Sn
Sn
BP0 a f g b
n bit/ BP
BP1 c
n1 f g x x
n2 e c x x
n3 d DP x x MSB abf LSB g e c d DP
1:2
Sn
1
multiplex
Sn Sn Sn
2 3
e d
DP
0 1 2 3
a b x x
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1:3 multiplex 1:4 multiplex
1 2 f
a b g e d c DP Sn
BP0
n bit/ BP
BP1 BP2
n1 a d g x
n2 f e x x MSB b DP c a d g f LSB e
Sn
0 1 2 3
b DP c x
Sn f
a b g e c d DP BP1 BP3 BP0 BP2
n bit/ BP 0 1 2 3 a c b DP
n1 f e g d
MSB a c b DP f
LSB egd
Sn
1
Product specification
PCF8576
MBK389
x = data bit unchanged.
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
7 CHARACTERISTICS OF THE I2C-BUS 7.5 PCF8576 I2C-bus controller
PCF8576
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer (see Fig.12)
The PCF8576 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally connected to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are connected to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. In the power-saving mode it is possible that the PCF8576 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8576 forces the SCL line to LOW until its internal operations are completed. This is known as the `clock synchronization feature' of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. 7.6 Input filters
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 7.2 START and STOP conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 7.3 System configuration (see Fig.14)
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. 7.4 Acknowledge (see Fig.15)
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.7 I2C-bus protocol
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576. The least significant bit of the slave address that a PCF8576 will respond to is defined by the level connected at its input pin SA0. Therefore, two types of PCF8576 can be distinguished on the same I2C-bus which allows: * Up to 16 PCF8576s on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex on the same I2C-bus. The I2C-bus protocol is shown in Fig.16. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8576 slave addresses available. All PCF8576s with the corresponding SA0 level acknowledge in parallel with the slave address but all PCF8576s with the alternative SA0 level ignore the whole I2C-bus transfer.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8576s. The last command byte is tagged with a cleared most significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8576s on the bus. After the last command byte, a series of display data bytes (n) may follow. These display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8576 device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8576. After the last display byte, the I2C-bus master issues a STOP condition (P). 7.8 Command decoder
PCF8576
The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position (Fig.17). When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates the last command byte of the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8576 are defined in Table 5.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.12 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.13 Definition of START and STOP conditions. 1998 Feb 06 20
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.14 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.15 Acknowledgement on the I2C-bus.
1998 Feb 06
21
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
handbook, full pagewidth
R/ W slave address S
acknowledge by all addressed PCF8576s
acknowledge by A0, A1 and A2 selected PCF8576 only
S 0 1 1 1 0 0A 0AC
0 1 byte n
COMMAND
A
DISPLAY DATA
A
P
1 byte(s)
n
0 byte(s) update data pointers and if necessary, subaddress counter
MBK279
Fig.16 I2C-bus protocol.
MSB C REST OF OPCODE
LSB
MSA833
C = 0; last command. C = 1; commands continue.
Fig.17 General format of command byte.
1998 Feb 06
22
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 5 Definition of PCF8576 commands OPCODE C1 0 LP E B M1 M0 OPTIONS Table 6 Table 7 Table 8 DESCRIPTION Defines LCD drive mode. Defines LCD bias configuration.
PCF8576
COMMAND MODE SET
Defines display status. The possibility to disable the display allows implementation of blinking under external control. Defines power dissipation mode. Six bits of immediate data, bits P5 to P0, are transferred to the data pointer to define one of forty display RAM addresses. Three bits of immediate data, bits A2 to A0, are transferred to the subaddress counter to define one of eight hardware subaddresses. Defines input bank selection (storage of arriving display data). Defines output bank selection (retrieval of LCD display data). The BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. Defines the blinking frequency. Selects the blinking mode; normal operation with frequency set by BF1, BF0 or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes. MODE SET option 4 MODE BIT LP 0 1
Table 9 LOAD DATA C 0 P5 P4 P3 P2 POINTER DEVICE SELECT BANK SELECT C1 1 0 0 A2 P1 P0 Table 10
A1
A0
Table 11
C1
1
1
1
0
I
O
Table 12 Table 13
BLINK
C1
1
1
0
A
BF1 BF0
Table 14 Table 15
Table 6
MODE SET option 1 LCD DRIVE MODE BITS M1 0 1 1 0 M0 1 0 1 0
Table 9
DRIVE MODE Static 1:2 1:3 1:4 Table 7
1 1
BACKPLANE 1 BP MUX (2 BP) MUX (3 BP) MUX (4 BP)
Normal mode Power-saving mode Table 10 LOAD DATA POINTER option 1 DESCRIPTION
BITS
6-bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 MODE SET option 2 LCD BIAS
3bias 2bias
BIT B 0 1
Table 11 DEVICE SELECT option 1 DESCRIPTION 3-bit binary value of 0 to 7 A2 BITS A1 A0
Table 8
MODE SET option 3 BIT E 0 1
Table 12 BANK SELECT option 1 STATIC RAM bit 0 RAM bit 2 1 : 2 MUX RAM bits 0 and 1 RAM bits 2 and 3 BIT I 0 1
DISPLAY STATUS Disabled (blank) Enabled
1998 Feb 06
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 13 BANK SELECT option 2 STATIC RAM bit 0 RAM bit 2 1 : 2 MUX RAM bits 0 and 1 RAM bits 2 and 3 BIT O 0 1 7.10 Cascaded operation
PCF8576
Table 14 BLINK option 1 BITS BLINK FREQUENCY BF1 Off 2 Hz 1 Hz 0.5 Hz Table 15 BLINK option 2 BLINK MODE Normal blinking Alternation blinking 7.9 Display controller BIT A 0 1 0 0 1 1 BF0 0 1 0 1
In large display configurations, up to 16 PCF8576s can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). When cascaded PCF8576s are synchronized so that they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8576s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.18). The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8576s. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when PCF8576s with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8576 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8576 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig.19. For single plane wiring of packaged PCF8576s and chip-on-glass cascading, see Chapter 12.
The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8576 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
handbook, full pagewidth
VDD SDA 1 SCL 2 SYNC CLK 3 5
VLCD 12 17 to 56
40 segment drives
LCD PANEL
PCF8576
13, 15 14, 16 7 A0 8 A1 9 A2 10 11 SA0 VSS (up to 2560 elements) BP0 to BP3 (open-circuit)
4 OSC 6
V LCD VDD tr 2CB 5 HOST MICROPROCESSOR/ MICROCONTROLLER SDA SCL SYNC CLK OSC 1 2 3 4 6 7 VSS A0 8 A1 9 A2 10 11
R
V DD
V 12
LCD
17 to 56 40 segment drives
PCF8576
13, 15 14, 16
4 backplanes
BP0 to BP3
MBK280
SA0 V SS
Fig.18 Cascaded PCF8576 configuration.
1998 Feb 06
25
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
handbook, full pagewidth
1 Tframe = f frame
BP0
SYNC (a) static drive mode. BP1 (1/2 bias)
BP1 (1/3 bias)
SYNC (b) 1 : 2 multiplex drive mode.
BP2
SYNC (c) 1 : 3 multiplex drive mode.
BP3
SYNC
MBE535
(d) 1 : 4 multiplex drive mode.
Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance of the SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may be countered by an external pull-up resistor.
Fig.19 Synchronization of the cascade for the various PCF8576 drive modes.
1998 Feb 06
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI VO II IO IDD, ISS, ILCD Ptot PO Tstg 9 HANDLING supply voltage LCD supply voltage input voltage SDA, SCL, CLK, SYNC, SA0, OSC, A0 to A2 output voltage S0 to S39, BP0 to BP3 DC input current DC output current VDD, VSS or VLCD current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 VDD - 11.0 VSS - 0.5 VLCD - 0.5 - - - - - -65 MAX. +11.0 VDD
PCF8576
UNIT V V V V mA mA mA mW mW C
VDD + 0.5 VDD + 0.5 20 25 50 400 100 +150
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ).
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
10 DC CHARACTERISTICS VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD - 2 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD supply voltage LCD supply voltage supply current normal mode power-saving mode note 1 note 2 fclk = 200 kHz fclk = 35 kHz; VDD = 3.5 V; VLCD = 0 V; A0, A1 and A2 connected to VSS - - - - 180 60 A A 2 VDD - 9 - - 9 V VDD - 2 V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Logic VIL VIH VOL VOH IOL1 IOH1 IOL2 IL1 IL2 Ipd RSYNC VPOR CI VBP VS RBP RS Notes 1. VLCD VDD - 3 V for 13bias. 2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 3. Resets all logic when VDD < VPOR. 4. Periodically sampled, not 100% tested. 5. Outputs measured one at a time. LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current CLK, SYNC HIGH-level output current CLK LOW-level output current SDA and SCL leakage current SA0, A0 to A2, CLK, SDA and SCL leakage current OSC A0, A1, A2 and OSC pull-down current pull-up resistor (SYNC) Power-on reset voltage level input capacitance note 3 note 4 IOL = 0 mA IOH = 0 mA VOL = 1 V; VDD = 5 V VOH = 4 V; VDD = 5 V VOL = 0.4 V; VDD = 5 V VI = VDD or VSS VI = VDD VI = 1 V; VDD = 5 V VSS 0.7VDD - 1 1 3 - - 20 20 - - - - - - - - - - - - - - 50 50 1.0 - 0.3VDD VDD 0.05 - - - - 1 1 150 150 1.6 7 - - 5 7.5 V V V V mA mA mA A A A k V pF
VDD - 0.05 -
LCD outputs DC voltage component BP0 to BP3 DC voltage component S0 to S39 output resistance BP0 to BP3 output resistance S0 to S39 CBP = 35 nF CS = 5 nF note 5; VLCD = VDD - 5 V note 5; VLCD = VDD - 5 V 20 20 - - mV mV k k
1998 Feb 06
28
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
11 AC CHARACTERISTICS VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD - 2 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fclk PARAMETER oscillator frequency on pin CLK normal mode power-saving mode tclkH tclkL tPSYNC tSYNCL tPLCD CLK HIGH time CLK LOW time SYNC propagation delay time SYNC LOW time driver delays with test loads VDD = 5 V; note 1 VDD = 3.5 V see Fig.21 125 21 1 1 - 1 VLCD = VDD - 5 V; see Fig.20 - - 4.7 4.0 4.7 4.7 4.0 - - - 250 0 4.0 200 31 - - - - - - - - - - - - - - - - - 288 48 - - 400 - 30 kHz kHz s s ns s s CONDITIONS MIN. TYP. MAX. UNIT
Timing characteristics: I2C-bus; note 2; see Fig.22 tSW tBUF tHD;STA tSU;STA tLOW tHIGH tr tf CB tSU;DAT tHD;DAT tSU;STO Notes 1. At fclk < 125 kHz, I2C-bus maximum transmission speed is derated. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. tolerable spike width on bus bus free time START condition hold time set-up time for a repeated START condition SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time capacitive bus line load data set-up time data hold time set-up time for STOP condition 100 - - - - - 1 0.3 400 - - - ns s s s s s s s pF ns ns s
SYNC
6.8 (2%) 3.3 k (2%) 1 nF
V DD
CLK
0.5VDD
SDA, SCL
1.5 k (2%)
VDD
BP0 to BP3, and S0 to S39
VDD
MBE544
Fig.20 Test loads.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
handbook, full pagewidth
1/ f clk t clkH t clkL 0.7VDD 0.3VDD
CLK
SYNC
0.7VDD 0.3VDD t PSYNC t PSYNC t SYNCL 0.5 V (VDD = 5 V) 0.5 V t PLCD
MBE545
BP0 to BP3, and S0 to S39
Fig.21 Driver timing waveforms.
ndbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.22 I2C-bus timing waveforms.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
11.1 Typical supply current characteristics
PCF8576
50 I SS (A) 40
MBE530
MBE529
50 normal mode I LCD (A) 40
30
30
20 power-saving mode 10
20
10
0 0 100 f frame (Hz) 200
0 0 100 f frame (Hz) 200
VDD = 5 V; VLCD = 0 V; Tamb = 25 C.
VDD = 5 V; VLCD = 0 V; Tamb = 25 C.
Fig.23 -ISS as a function of fframe.
Fig.24 -ILCD as a function of fframe.
handbook, halfpage
50
MBE528 - 1
MBE527 - 1
I SS (A) 40 normal mode f clk = 200 kHz
handbook, halfpage
50
I LCD
(A) 40
85 C
o
30
30 25 C
o
20
20
o
10
power-saving mode f clk = 35 kHz
40 C 10
0 0 5 V DD (V) 10
0 0 5 V DD (V) 10
VLCD = 0 V; external clock; Tamb = 25 C.
VLCD = 0 V; external clock; fclk = nominal frequency.
Fig.25 ISS as a function of VDD.
Fig.26 ILCD as a function of VDD.
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
11.2 Typical characteristics of LCD outputs
PCF8576
MBE532 - 1
handbook, halfpage
10
2.5 R O(max) (k) 2.0 RS
MBE526
R
O(max) (k) RS
1.5 1 R BP 1.0 R BP
0.5
10
-1
0
3
VDD (V)
6
0 40
0
40
80
120 o Tamb( C)
VLCD = 0 V; Tamb = 25 C.
VDD = 5 V; VLCD = 0 V.
Fig.27 RO(max) as a function of VDD.
Fig.28 RO(max) as a function of Tamb.
1998 Feb 06
32
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dbook, full pagewidth
1998 Feb 06
SDA SCL SYNC CLK V DD OSC A0 A1 A2 SA0 V SS V LCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26
12 APPLICATION INFORMATION
Philips Semiconductors
SDA SCL SYNC CLK V DD VSS V LCD 1 2 3 4 5 6 7 8 9 10 11 12 BP0 BP2 open BP1 BP3 S40 S41 S42 S43 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61
Universal LCD driver for low multiplex rates
33
S0 backplanes S10
PCF8576T
15 16 17 18 19 20 34 S7 S8 S9 S10 S11 S11 24 25 26 27 28 33 32 31 30 29 S17 S16 S15 S14 S13 S12 S12 S13 S39 segments S40 42 41 40 39 38 S25 S24 S23 S22 S21
PCF8576T
15 16 17 18 19 20 34 S47 S48 S49 S50 S51 24 25 26 27 28 33 32 31 30 29 S57 S56 S55 S54 42 41 40 39 38
Product specification
S53 S52 S52 S53 S79
MBK281
PCF8576
S50
S51
Fig.29 Single plane wiring of packaged PCF8576Ts.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
12.1 Chip-on-glass cascadability in single plane
PCF8576
and the backplane output pads. The only bus line that does not require a second opening to lead through to the next PCF8576 is VLCD, being the cascade centre. The placing of VLCD adjacent to VSS allows the two supplies to be connected together. When an external clocking source is to be used, OSC of all devices should be connected to VDD. The pads OSC, A0, A1, A2 and SA0 have been placed between VSS and VDD to facilitate wiring of oscillator, hardware subaddress and slave address.
In chip-on-glass technology, where driver devices are bonded directly onto glass of the LCD, it is important that the devices may be cascaded without the crossing of conductors, but the paths of conductors can be continued on the glass under the chip. All of this is facilitated by the PCF8576 bonding pad layout (see Fig.30). Pads needing bus interconnection between all PCF8576s of the cascade are VDD, VSS, VLCD, CLK, SCL, SDA and SYNC. These lines may be led to the corresponding pads of the next PCF8576 through the wide opening between VLCD pad 13 BONDING PAD LOCATIONS
S17
S16
S15
S14
S13
S12
S11
S9
S8
S7
S6
S5
22
34
33
32
31
30
29
28
27
26
25
24
23
21 20 19
S4 S3 S2 S1 S0 BP3 BP1 BP2 BP0
18 17 16 15 14 13
handbook, full pagewidth
S18 S19 S20 S21 S22 S23 S24 S25 4.12 mm S26 S27 S28 S29 S30 S31 S32 S33
35 36 37 38 39 40 41 42
x 0
43 44 45 46 47 48 49 10 50 51 52 53 54 55 56 1 2 3 4 5 6 7 9 8
0 y
PCF8576
cascade centre 12
11
S10
VLCD VSS SA0 A2
SYNC
SDA
OSC
S34
S35
S36
S37
S38
S39
SCL
CLK
A0
3.07 mm
MBK282
Bonding pad dimensions: 120 x 120 m.
Fig.30 Bonding pad locations.
1998 Feb 06
34
VDD
A1
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 16 Bonding pad locations (dimensions in m) All x/y coordinates are referenced to centre of chip (see Fig.30). SYMBOL SDA SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 x -155 45 245 445 645 865 1105 1375 1375 1375 1375 1375 1375 1375 1375 1375 1375 1375 1375 1375 1375 1105 865 645 445 245 45 -155 y -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1700 -1500 -1300 -1100 300 500 700 900 1100 1300 1500 1700 1900 1900 1900 1900 1900 1900 1900 1900 SYMBOL S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 PAD 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 x -355 -555 -755 -955 -1155 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1375 -1155 -955 -755 -555 -355
PCF8576
y 1900 1900 1900 1900 1900 1900 1660 1420 1200 1000 800 600 400 200 -200 -400 -600 -800 -1000 -1200 -1420 -1660 -1900 -1900 -1900 -1900 -1900 -900
1998 Feb 06
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
14 PACKAGE OUTLINE VSO56: plastic very small outline package; 56 leads
PCF8576
SOT190-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 e 0.75 HE 15.8 15.2 L 2.25 Lp 1.6 1.4 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55
0.017 0.0087 0.85 0.012 0.0055 0.84
0.44 0.62 0.0295 0.43 0.60
0.063 0.089 0.055
0.057 0.035 0.008 0.004 0.004 0.051 0.022
7 0o
o
Note 1. Plastic or metal protrusions of 0.3 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-04-02 97-08-11
1998 Feb 06
36
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
15 SOLDERING 15.1 Introduction 15.3 Wave soldering
PCF8576
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Reflow soldering
Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Repairing soldered joints
Reflow soldering techniques are suitable for all VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Feb 06
37
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8576
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 06
38
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
NOTES
PCF8576
1998 Feb 06
39
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/03/pp40
Date of release: 1998 Feb 06
Document order number:
9397 750 03252

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